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rev. 1.2 4/16 copyright ? 2016 by silicon laboratories SI3402Biso-evb SI3402Biso-evb i solated e valuation b oard for the SI3402B 1. description the SI3402B isolated evaluation board (SI3402Biso-evb rev 2) is a reference design for power supplies in power over ethernet (poe) powered device (pd) applicatio ns. the SI3402B is described more completely in the data sheet and application notes. this document desc ribes only the SI3402Biso-evb evaluation board. an evaluation board demonstrating the non-isolated applic ation is described in the SI3402B-evb user?s guide. 2. planning for successful designs silicon labs strongly recommends the use of the schematic and la yout databases provid ed with the evaluation boards as the starting point for your design. use of external components other than those described and recommended in this document is generally discouraged. refer to table 2 on page 9 for more information on critical component specifications. ca reful attention to the recommended layout guidelines is required to enable robust designs and full specification compliance. to hel p ensure design success, please submit your schematic and layout databases to www.silabs.com/support for review and feedback. 3. SI3402B bo ard interface ethernet data and power are applied to the board thro ugh the rj-45 connector (j1). the board itself has no ethernet data transmission functionality, but, as a conveni ence, the ethernet transformer secondary is brought out to the test points. power may be applied in the following ways: ? connecting a dc source to pins 1, 2 and 3, 6 of the ethernet cable (either polarity). ? connecting a dc source to pins 4, 5 and 7, 8 of the ethernet cable (either polarity). ? using an ieee 802.3-2 015-compliant, po e-capable pse, such as trendnet tpe-1020ws. the SI3402Biso-evb board schematics and layout are shown in figures 1 through 6. the dc output is at connectors j11(+) and j12(?). boar ds are generally shipped configured to produce +5 v output voltage but can be configured for +3.3 v or other output voltages as shown in table 2 on page 9. the preconfigured class 3 signature also can be modified ac cording to table 3 on page 10. the d8?d15 schottky-type diode bridge bypass is recommended only for higher power levels (class 3 operation). for lower power levels, such as class 1 and class 2, the diodes can be removed. when the SI3402B is used in external diode bridge configuration, it requires at least one pair of the ctx and spx pins to be connected to the poe voltage input terminals (to the input of the external bridge). the feedback loop compensation has been optimized for 3.3, 5, 9, and 12 v output as well as with standard and low esr capacitors in the output filter section (table 2 on page 9). the use of low esr capacitors is recommended for lower output ripple, improved load transient re sponse and low temperature (below 0 c) operation.
SI3402Biso-evb 2 rev. 1.2 400 w cesar chavez st, austin, tx 78701, united states vneg is a thermal plane as well as esd and emi. use thermal vias to at least 1 inch square plane on backside 1 to 1.2mm pitch 0.3 to 0.33mm diameter. 10:3 secondary cathode anode j1:a1, k1 must be isolated from a2,k2 rdp ct rdn tdp tdn capacitors c10-c17 are for esd immunity.. place optional bypass diodes for high power applications (>7w) in parallel. vpos is an emi and esd plane. use top layer. connect transformer and input filter caps together minimizing area of return loop and then connect to vpos plane. vout pos plane for emi 5v at least one pair of ct1/ct2 or sp1/sp2 should be connected. vss vss 0 gndi gndi gndi c6 100uf u3 tlv431 l3 330 ohm l4 330 ohm c20 1nf d9 ss2150 c15 1nf d14 ss2150 t1 fa2924 2 9 1 7 8 10 c19 1nf c11 1nf c18 0.1uf c12 1nf c10 1nf + c2 12uf r3 48.7 c3 1uf d3 pds1040 d2 dflt30a-7 d1 1n4148w r11 4.99k l5 330 ohm c13 1nf c22 0.1uf u2 vo618a-3x017t r4 24.3k r7 2.05k d13 ss2150 c4 1uf tp2 swo ni r5 36.5k r10 10 l2 330 ohm c14 1nf d11 ss2150 r6 12.1k u1 SI3402B erout 1 nc 2 vdd 3 nc 4 nploss 5 rdet 6 hso 7 rcl 8 vneg 9 sp2 10 sp1 11 vpos 12 ct2 13 ct1 14 vssa 15 nc 16 nc 17 swo 18 vss2 19 fb 20 + c5 1000uf j1 rj-45 mx0+ 1 mx0- 3 mx1+ 4 pwr2 8 pwr3 9 pwr4 10 ct 2 led_k2 k2 led_a2 a2 led_k1 k1 led_a1 a1 pwr1 7 ct/mx1- 5 mx1- 6 pwr5 11 r1 330 c7 470pf l1 1uh c21 15nf tp7 ni c17 1nf j12 bnd_post r12 0 c9 3.3nf tp6 ni r8 0 tp3 ni tp1 vposs ni d8 ss2150 tp5 ni r2 49.9k j11 bnd_post d10 ss2150 tp4 ni d12 ss2150 c16 1nf d15 ss2150 c1 1uf figure 1. SI3402B schematic?5 v, class 3 pd
SI3402Biso-evb rev. 1.2 3 figure 2. SI3402B layout (top layer)
SI3402Biso-evb 4 rev. 1.2 figure 3. primary side (layer 2)
SI3402Biso-evb rev. 1.2 5 figure 4. internal 1 (layer 3)
SI3402Biso-evb 6 rev. 1.2 figure 5. internal 2 (layer 4)
SI3402Biso-evb rev. 1.2 7 figure 6. secondary side (bottom layer)
SI3402Biso-evb 8 rev. 1.2 4. bill of materials the following bill of materials is for a 5 v class 3 design. for class 1 and class 2 designs, in ad dition to updating the classification resistor (r3), the external diode bridge (d8?d15) can be removed to reduce bom costs. tables 2 and 3 list changes to the bill of material s for other output voltages and classi fication levels. refer to ?an956: using the SI3402B poe pd controller in isolated and non-isolated designs? for more information. table 1. SI3402Biso-evb bill of materials qty value ref rating voltage tol type pcb footprint mfr part number mfr 3 1 f c1, c3, c4 100 v 10% x7r c1210 c1210x7r101-105k venkel 1 12 f c2 100 v 20% alum_elec c2.5x6.3mm-rad eeufc2a120 panasonic 1 1000 f c5 6.3 v 20% alum_elec c3.5x8mm-rad eca0jm102 panasonic 1 100 f c6 6.3 v 10% x5r c1210 c1210x5r6r3-107k venkel 1 470 pf c7 50 v 10% x7r c0805 c0805x7r500-471k venkel 1 3.3 nf c9 16 v 10% x7r c0805 c0805x7r160-332k venkel 8 1 nf c10, c11, c12, c13, c14, c15, c16, c17 100 v 10% x7r c0603 c0603x7r101-102k venkel 1 0.1 f c18 100 v 10% x7r c0805 c0805x7r101-104k venkel 2 1 nf c19, c20 3000 v 10% x7r c1808 c1808x7r302-102k venkel 1 15 nf c21 16 v 10% x7r c0805 c0805x7r160-153k venkel 1 0.1 f c22 16 v 10% x7r c0805 c0805x7r160-104k venkel 1 1n4148w d1 2 a 100 v fast sod123 1n4148w diodes inc 1 dflt30a-7 d2 4.65 a 30 v zener powerdi-123 dflt30a-7 diodes inc. 1 pds1040 d3 10 a 40 v schottky powerdi-5 pds1040-13 diodes inc. 8 ss2150 d8, d9, d10, d11, d12, d13, d14, d15 2 a 150 v single do-214ac ss2150-ltp mcc 1 rj-45 j1 receptacle rj45-si-52004 si-52003-f bel 2 bnd_post j11, j12 15 a banana banana-jack 101 abbatron hh smith 1 1 h l1 2.9 a 20% shielded ind-6.6x4.45mm do1608c-102ml_ coilcraft 4330 ? l2, l3, l4, l5 1500 ma smt l0805 blm21pg331sn1 murata 1330 ? r1 1/10 w 1% thickfilm r0805 cr0805-10w-3300f venkel 1 49.9 k ? r2 1/10 w 1% thickfilm r0805 cr0805-10w-4992f venkel 1 48.7 ? r3 1/8 w 1% thickfilm r0805 crcw080548r7fkta vishay 1 24.3 k ? r4 1/8 w 1% thickfilm r0805 crcw080524k3fkea vishay 1 36.5 k ? r5 1/10 w 1% thickfilm r0805 cr0805-10w-3652f venkel 1 12.1 k ? r6 1/10 w 1% thickfilm r0805 cr0805-10w-1212f venkel 12.05k ? r7 1/16 w 1% thickfilm r0603 cr0603-16w-2051f venkel 20 ? r8, r12 2 a thickfilm r0805 cr0805-10w-000 venkel 11 0 ? r10 1/10 w 1% thickfilm r0805 cr0805-10w-10r0f venkel 14.99k ? r11 1/10 w 1% thickfilm r0805 cr0805-10w-4991f venkel 1 fa2924 t1 xfmr-fa2924 fa2924-al coilcraft 1 SI3402B u1 100 pd qfn20n5x5p0.8 SI3402B silicon labs 1 vo618a-3x017t u2 so4n10.16p2.54-akec vo618a-3x017t vishay 1 tlv431 u3 shunt tlv431-dbz tlv431bcdbzr ti not installed components 7 black tp1, tp2, tp3, tp4, tp5, tp6, tp7 loop testpoint 5001 keystone
SI3402Biso-evb rev. 1.2 9 table 2. component selection for other output voltages and filter types 3.3 v output transformer* ep10 fa2671 ep13fa2924al output rectifier: pds1040 snubber: r10, c7 10 w, 470 pf reference any tlv431 r5 r6 c6 c5 panasonic r7, r8, r12 c9,c21 standard esr output filter 24.3 k ? 14.7 k ? 100 f x5r 1000 f 6.3 v eca0jm102 500 ? , 1.1 k ? , 475 ? 10 nf, 33 nf, low esr output filter 24.3 k ? 14.7 k ? 100 f x5r 560 f 6.3 v eeufm0j561 324 ? , 2 k ? , 820 ? 10 nf, 100 n f 5.0 v output tr a n s f o r m e r * ep10 fa2671 ep13 fa2924cl output rectifier pds1040 snubber: r10, c7 10 ? , 470 pf reference any tlv431 r5 r6 c6 c5 panasonic r7, r8, r12 c9, c21 standard esr output filter 36.5 k ? 12.1 k ? 100 f x5r 1000 f 6.3 v eca0jm102 2.05 k ? , 0 ? , 0 ? 3.3 nf, 1 5 nf low esr output filter 36.5 k ? 12.1 k ? 100 f x5r 560 f 6.3 v eeufm0j561 2.05 k ? , 0 ? , 0 ? 3.3 nf, 33 nf 9.0 v output tr a n s f o r m e r * ep10 fa2672 ep13 fa2805cl output rectifier : pds5100 snubber: r10, c7 20 ? , 68 pf reference higher voltage e.g., tlv431asnt1g r5 r6 c6 c5 panasonic r1,r7, r8, r12 c9,c21 standard esr output filter 66.5 k ? 10.5 k ? 22 f x5r 16 v 470 f 16 v eca1m471 1.3 k ??? 3 k ? , 0 ? , 0 ? 10 nf, 15 nf low esr output filter 66.5 k ? 10.5 k ? 22 f x5r 16 v 330 f 16 v eeufm1c331 3 k ? , 0 ? , 0 ? 10 nf, 15 nf 12.0 v output transformer* ep10 fa2672 ep13 fa2805cl output rectifier: pds5100 snubber: r10, c7 20 ? , 68 pf reference higher voltage e.g., tlv431asnt1g r5 r6 c6 c5 panasonic r1,r7, r8, r12 c9,c21 standard esr output filter 88.7 k ? 10.2 k ? 22 f x5r 16 v 470 f 16 v eca1m471 1.3 k ??? 3 k ? , 0 ? , 0 ? 10 nf, 15 nf low esr output filter 88.7 k ? 10.2 k ? 22 f x5r 16 v 330 f 16 v eeufm1c331 1.3 k ??? 3 k ? , 0 ? , 0 ? 10 nf, 15 nf *note: coilcraft part number. ep13 core is recommended for >10 w output power.
SI3402Biso-evb 10 rev. 1.2 table 3. component selection for different classification levels class r3 (1%) 0o p e n 11 4 0 27 5 34 5 . 3
SI3402Biso-evb rev. 1.2 11 a ppendix ?SI3402Biso d esign and l ayout c hecklist introduction although all four evb design s are preconfigured as class 3 pds with 5 v outputs, th e schematics and layouts can easily be adapted to meet a wide variety of common output voltages and power levels. the complete evb design databases for the standard 5 v/class 3 conf iguration are included in the evb kit and can also be requested through s ilicon labs customer support at www.silabs.com/poe under the ?documentation? link. silicon labs strongly recommends using these evb sche matics and layout files as a starting point to ensure robust performance and to help avoid common mistakes in the schematic capture and pcb layout processes. following are recommended design checklists that can assist in trouble-free development of robust pd designs: refer also to the SI3402B data sheet and an956 when using the checklists below. 1. design planning checklist: a. silicon labs strongly recommends using the evb schem atics and layout files as a starting point as you begin integrating the SI3402B into your system design process. b. determine your load?s power requirements (i.e., v out and i out consumed by the pd, including the typical expected transient surge conditions). in ge neral, to achieve the highest overall efficiency performance of the si3402, choose the highest voltage used in your pd and then post regulate to the lower supply rails, if necessary. c. if your pd design consumes >7 w, make sure you bypass the si3402?s on-chip diode bridges with external schottky diode bridges or discrete sc hottky diodes. bypassing the si3402?s on-chip diode bridges with external bridges or discrete diodes is required to help spread the heat generated in designs dissipating > 7w. d. based on your required pd power level, select the app ropriate class resistor value by referring to table 3 of an956. this sets the rclass resistor (r3 in figure 1 on page 2). e. the feedback loop stability has b een checked over the entire load range for the specific component choices in table 1. low esr filter capacitors will gi ve better load transient response and lo wer output ripple so they are generally preferred. for the standard esr capacitor, the esr increase at very low temperatures may cause a loop stability issue. a ty pical evaluation board has been shown to exhibit instability under very heavy loads at ?20 c. due to se lf-heating, this condition is not a grea t concern. however, using a low esr filter capa citor solves this problem (but requires some recompensation of the feedback loop). silicon laboratories recommends against component subs titution in the filtering and feedback path as this may result in unstable operation. also, use care in situations that have additional capacitive loading as this will also affect loop stability. 2. general design checklist items: a. esd caps (c10?c17 in figure 1) are strongly recommended for designs where system-level esd (iec6100-4-2) must provide >15 kv tolerance. b. if your design uses an aux su pply, make sure to include a 3 ? surge limiting resistor in series with the aux supply for hot insertion. refe r to an956 when aux supply is 48 v. c. silicon labs strongly recommen ds the inclusion of a minimum load (250 mw) to avoid switcher pulsing when no load is present, and to avoid false discon nection when less than 10 ma is drawn from the pse. if your load is not at least 250 mw, add a resistor load to dissipate at least 250 mw. d. if using ploss function, make sure it?s properly te rminated for connection in your pd subsystem. if ploss is not needed, leave this pin floating.
SI3402Biso-evb 12 rev. 1.2 3. layout guidelines: a. make sure the vneg pin of the SI3402B is c onnected to the backside of the qfn package with an adequate thermal plane, as noted in the data sheet and an956. b. keep the trace length from connecting to swo an d retuning to vss1 and vss2 as short as possible. make all of the power (high current) traces as short, direct, and thick as possible. it is a good practice on a standard pcb board to make the traces an absolute minimum of 15 mils (0.381 mm) per ampere. c. usually one standard via handle s 200 ma of current. if the trace will need to conduct a significant amount of current from one plane to the other use multiple vias. d. keep the circular area of the loop from the swit cher fet output to the in ductor or transformer and returning from th e input filter capacitors (c1?c4 ) to vss2 as small a diameter as possible. also, minimize the circular area of the loop from the output of the inductor or transformer to the schottky diode and returning through the fist stage output filter capaci tor back to the inductor or transformer as small as possible. if possible, keep the direction of current flow in these two loops the same. e. connect the sense points to the output terminals dire ctly to avoid load regulati on issues related to ir drops in the pcb traces. the sense points are the output side of r5 and pin 3 of tlv431. f. keep the feedback and loop st ability components as far from the transformer/inductor and noisy power traces as possible. g. if the outputs have a ground plane or positive out put plane, do not connect the high current carrying components and the filter capacitors through the plane. connect them together and then connect to the plane at a single point. h. as a convenience in layout, please note that the ic is symmetrical with respect to ct1, ct2, sp1 and sp2. these leads can be interchanged. at least one pair of ct1/ct2 or sp1/sp2 should be connected. to help ensure first pass success, please su bmit your schematics and layout files to www.silabs.com/support for review. other technical questions may be submitted as well.
SI3402Biso-evb rev. 1.2 13 d ocument c hange l ist revision 1.1 to revision 1.2 ? initial release of si3402 biso-evb user?s guide, modified from si3402- iso-evb user?s guide revision 1.1.
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